1. Field of the Invention
This invention is related to the field of integrated circuit testing, and more particularly, to structural testing of multi-core integrated circuits, such as multi-core microprocessors.
2. Description of the Related Art
ICs of low to moderate complexity may typically be tested using functional tests. In some cases test vectors may be developed to exercise all of the functional characteristics of the specific IC and used in manufacturing to validate each unit. Many ICs, such as chip multiprocessors (CMP) may be too complex for this approach, and the collection of functional test vectors that would be required for functional testing may be much too large for available automated test equipment (ATE).
Most ICs comprise a collection of independent or quasi-independent functional blocks and in some instances it may be more efficient to test each block separately, rather than testing the chip as a whole. This test method is called structural testing, because it tests whether circuit structures have been correctly manufactured. In order to perform structural testing on an IC, the facility may input the appropriate test vectors to the structural block that is to be tested and obtain the resulting output. New structures may need to be inserted into the IC specifically to support testing, for example MUXD or LSSD scan cells.
Structural tests may attempt to verify that all structural blocks and the interconnections between blocks are manufactured properly. Using a gate-level representation of the design, an automated test pattern generator (ATPG) may algorithmically calculate stimulus for controllable nodes such that the internal design structures may be tested. The complexity and size of designs may make “controlling” and “observing” each structure exceedingly difficult. Two test methodologies; “scan testing” and “random testing” may be selected depending upon the exact nature of the design to be tested.
In full scan testing, storage elements within the device under test (DUT) may be connected together into one or more scan chains. The ATPG patterns may be stored in the tester memory of the ATE. The ATE may output the vectors into the circuit using a number of parallel scan chains. Factors such as availability of chip I/O pins, availability of tester channels, and on-chip routing congestion caused by chaining storage elements in test mode may place a limit on the number of scan chains which can be used.
The random test methodology applies random (or pseudo-random) data values to the design-input nodes, to exercise each structure in the design (in effect, randomly controlling and observing them). This method may yield better results when testing regular structures, such as memories. The quality of pseudorandom patterns may be increased with the custom design of LFSRs (linear-feedback shift registers) and phase shifters. Desired segments of the available random pattern space may be generated by loading the LFSR with specific seeds from which to start pattern generation. A MISR (multiple-input signature register) may be used to capture the responses to the random patterns.
However, some designs may unsuitable for testing using random patterns. For these designs, test points may need to be inserted to improve controllability and observability of internal structures. In the BIST (built-in-self-test) methodology for logic, the LFSR and MISR may become part of the chip itself. BIST may implement a full-scan methodology to apply random pattern data to each logic structure. This architecture may allow for many more parallel scan chains, because they no longer have to be routed to chip I/O pins.
Typically, logic BIST uses scan technology as its base. A PRPG (pseudo-random pattern generator) replaces a deterministic ATPG to generate the test patterns. The test patterns may be input through the scan chains and the core logic, and an MISR (multiple-input signature register) may be used to collect the responses. All circuitry required for the PRPGs and the MISRs may be embedded on the chip. Embedded test-pattern generation and response-analysis may require little memory on the ATE.
One of the greatest virtues of BIST may be its ability to run test patterns at the rated functional speed of the chip under test, which may be crucial for time-sensitive designs. Because both test-pattern generation and response-analysis functions reside on the chip, the ATE is only required to trigger the test and therefore, its limitations may not constrain test execution. However, the amount of additional hardware added to the chip to perform a comprehensive BIST may be prohibitive.
Some complex ICs may be designed to include multiple copies of a functional block or core. For example a multi-core microprocessor may include multiple copies of a complex general-purpose processing core where each core functions independently, or nearly independently of the other cores. Traditionally, structural tests have been designed to test each core separately. Due to pin limitations, only one core may be tested at a time.